下世代技術節點的材料、製程、元件及電路熱模擬之關鍵技術
High Mobility Materials, Process, Stacked Channels, and Thermal Circuit Simulation
計畫團隊成員 Members 劉致為特聘教授
Distinguished Prof.
Chee Wee Liu
國立臺灣大學電子所
GIEE, NTU
李敏鴻教授
Prof. Min-Hung Lee
國立臺灣師範大學光電所
IEO, NTNU
陳敏璋教授
Prof. Miin-Jang Chen
國立臺灣大學材料系
MSE Dept., NTU
Category
Semiconductor, CMOS, 5G, Deep Learning, Edge Intelligence, Autonomous Cars, Atomic Layer Engineering
技術亮點
Technical Highlights
本計畫以研發3奈米以下之先進製程的材料、製程及元件,以利智慧終端應用中即時的計算之需求。鍺(鍺矽)有比應變矽通道更高的載子遷移率,環繞式電晶體因為具有更優於鰭式電晶體的控制能力,並搭配三維堆疊的架構以提升電流,實現高效能及低功耗的電路。最佳化磊晶、通道截面設計、摻雜設計、閘極堆疊、考慮載子遷移率之電流計算,以及元件/電路層級的自發熱效應分析等等,並加入鐵電材料與原子層工程,以完成環繞式通道之電晶體設計。
Ge/GeSi is used for the channels in this project and it is a promising material for beyond 3nm node due to its high mobility. GAA have superior gate control and the ION can be boost by channel stacking. Co-optimization of epitaxy, channel cross-section, doping, gate stack, mobility, self-heating, FE material, atomic layer engineering is studied for the device design.